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A Semiconductor industry Design for Test (DFT) Engineer will take responsibility for driving the design implementation and simulations through to successful tape-out for an innovative Semiconductor start-up revolutionizing the electronics industry.

The Semiconductor DFT Engineer will bring:

* Minimum of a good Bachelors degree in Electronics or similar discipline.

* 5+ years Design For Test (DFT) experience.

* Experience with MBIST insertion and verification on RTL and Gate level Netlist.

* Experience with Scan insertion.

* Good knowledge of Verilog HDL.

* Hands-on experience using EDA tools for DFT such as Cadence, Mentor or Synopsys.

* STA DFT test mode timing constraint development and analysis.

* TCL or Python Scripting.

The DFT Engineer role: The successful DFT Engineer will drive architectures, methodologies and tool flows for complex multi-million gate designs. With a good understanding of ATE, you’ll drive the test engineering team for successful Silicon bring up and test program development; will define the test plans and develop functional tests for final/wafer test program development.

A generous salary will be offered depending on your level of experience with Shares, Hybrid working, 25 days holiday, Private medical Cover and flexible working.

This company ensures diversity and inclusion for all, as well prioritizing the well-being of all employees. They encourage and support career development